New Family Of Chips Introduced From Cirrus Logic

15-Jan-04

Cirrus Logic Inc. announced the introduction of the CS49500 family, a high-end, multichannel audio, and digital signal processor (DSP) family targeted for the audio/video receiver (AVR) and other digital entertainment markets. The CS49500 family relies on dual 32-bit DSP cores, optimized for audio, with dual multiply-and-accumulate (MAC) units and 72-bit accumulators, to deliver up to 1,440 MOPS (millions of operations per second) for advanced decoding and 96 kHz multi-channel post processing. Without requiring any external RAM, the CS49500 family of single-chip solutions can support all industry-standard decoding algorithms, such as DolbyÆ Digital Pro-Logic IIx, DTS-ES 96/24 with THX and other advanced post-processing, in addition to customer-programmable algorithms. The CS49500 family has enough ROM to store all mainstream application codes and also supports extension to future algorithms via external download of code into RAM. The highlight of the CS49500 family is its dual decoder CS49520, which can, for example, simultaneously decode DTS and Dolby Digital, or AAC and Dolby Digital. The dual core architecture can operate as two separate 32-bit DSPs with different clock domains. Dual-decoding is an advanced feature that enables new AVRs to support dual zones with content coming from two different sources. The result is a powerful yet cost-effective solution for manufacturers of high-performance digital consumer entertainment systems such as AVRs and DVD receivers, digital televisions, home-theater systems, and other types of audio systems, such as automotive. Conventional DSP solutions use a single-core architecture that requires all audio code to be integrated together and operate in a tightly coupled, pre-defined manner. Using the Cirrus dual-core architecture and software framework, customers receive pre-certified software on the first core that covers all major technology standards for decoding and processing. Using the Cirrus C compiler and assembler, customers can easily develop code on the second core on top of Cirrus pre-certified post-processing features. Application interaction problems, which are inherent to development on a single core, are not a concern, because there is minimal coupling between the applications on different cores limited to only a data hand-off. The devices are available in a 144-pin LQFP package and are currently sampling. The CS49500 will be available at $12.95 when purchased in quantities of 10,000 or more. For more information, please visit www.cirrus.com.

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