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Silicon Magic Introduces Industry's First Chip-Multi-Processor Architecture With Embedded DRAM
Silicon Magic Corp. introduced DVine, the semiconductor industry's first Chip-Multi-Processor (CMP) architecture that enables OEMs to implement system-on-chip (SOC) devices for next-generation consumer electronics products. For OEMs adopting DVine in their products, the benefits include: higher performance and efficient space/area utilization through SOC integration; flexibility, scalability and programmability; greater design reusability and productivity; and faster time to market. The DVine (DRAM Vector engine) architecture combines a modular hardware architecture with an integrated software development environment to enable rapid SOC-based product development. The basic architecture integrates multiple Computing Modules (CMs) with an appropriate amount of high-performance, embedded DRAM as dictated by the target application. Each identical CM combines both scalar and vector processors for optimal performance in media-centric processing applications such as camcorders, DVR (Digital Video Recorders) players, and information appliances. DVine's CMP architecture with embedded DRAM allows faster development cycles than traditional ASICs and greater reusability than designs assembled from discrete processor and memory devices. Based on Symmetrical Multi-Processor (SMP) architecture with Single Instruction Multiple Data (SIMD) extensions, this unique approach provides superior scalability over both monolithic RISC/CISC architectures and more specialized ""media processor"" architectures. OEMs can expand their product functionality and performance by simply adding CMs and embedded DRAM as necessary to their SOC designs. The DVine architecture employs a shared-memory SMP programming model to support rapid software development and migration to successor products. Significant software engineering advantages are gained from this programming model, which is easy to understand and write, simple to debug, and readily extendible. Application adaptability differentiates this architecture from other offerings on the market. Programmability coupled with the ability to scale the amount of processing power and embedded DRAM enables SOC implementations of the DVine architecture that can be easily adapted to different applications such as DVR, R-DVD and HDTV. The architecture is well suited for different audio/video compression algorithms such as JPEG, MPEG-1, MPEG-2, MPEG-4, Dolby Digital and AAC. Further, OEMs can offer product differentiation by programming DVine for new features for proprietary video post-processing and pre-processing enhancements.